High voltage metal oxide semiconductor device

ABSTRACT

A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of patent application Ser. No.11/163,219, filed on Oct. 11, 2005. The entirety of the above-mentionedpatent application is hereby incorporated by reference herein and made apart of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a high voltage metaloxide semiconductor device.

2. Description of the Related Art

As the dimension of metal oxide semiconductor device continues toshrink, the resulting shorter channel length leads to an increase in theoperating speed of the transistor. However, other problems related tothe shorter channel grouped under the so-called ‘short channel effect’intensify. If the applied voltage remains unchanged but the transistorchannel length is reduced, the energy of the electrons inside thechannel will increase due to the acceleration by the electric fieldaccording to the basic formula: electric field=voltage/length. As aresult, the chance of electrical breakdown will increase. Furthermore,the increase in the intensity of the electric field will also lead to anincrease in the energy of the electrons within the channel andultimately result in an electrical breakdown.

In high power devices, double-diffused metal oxide semiconductor (DMOS)is an important device capable of handling high input voltage. Ingeneral, the DMOS device can be categorized into lateral double-diffusedMOS (LDMOS) and vertical double-diffused MOS (VDMOS).

FIG. 1 is a schematic cross-sectional view of a conventional LDMOS. Asshown in FIG. 1, the LDMOS device mainly comprises a substrate 100, afield oxide layer 102, a gate dielectric layer 104, a gate 106, anN-type drift region 108, an N-type drain region 110, a P-type well 112and an N-type source region 114. The substrate 100 is an N-typesubstrate (or a P-type substrate). The field oxide layer 102 is disposedin the substrate 100. The gate dielectric layer 104 is disposed in thesubstrate 100 adjacent to the field oxide layer 102. The gate 106 isdisposed on the gate dielectric layer 104 and a portion of the fieldoxide layer 102. The N-type drift region 108 is disposed in thesubstrate 100 under the field oxide layer 102. The N-type drain region110 is disposed in the substrate 100 on one side of the gate 106 closeto the field oxide layer 102. The P-type well 112 is disposed in thesubstrate 100 on another side of the gate 106. The N-type source region114 is disposed in the P-type well 112.

To meet the demand in high voltage applications, the N-type drain region108 of the LDMOS device is doped lightly to reduce dopant concentration.However, this method has limited capacity for increasing the operatingvoltage. Moreover, the driving current will be reduced as well.

FIG. 2 is a schematic cross-sectional view of a conventional VDMOSdevice. As shown in FIG. 2, the VDMOS device mainly comprises asubstrate 200, an N-type epitaxial layer 202, a gate dielectric layer204, a gate 206, an N-type source region 208, a P-type well 210 and aninsulating layer 212. The substrate 200 is an N-type substrate. TheN-type epitaxial layer 202 is disposed on the substrate 200. The gatedielectric layer 204 is disposed on the N-type epitaxial layer 202. Thegate 206 is disposed on the gate dielectric layer 204. The N-type sourceregion 208 is disposed in the P-type well 210 on each side of the gate206. The insulating layer 212 covers the gate 206.

In the VDMOS device, the variation in the equipotential betweenneighboring P-type wells 210 is rather large. Hence, the breakdownvoltage of the VDMOS device will be reduced. In fact, the highestoperating voltage is in the vicinity between 60˜100V, which is asignificant limitation on power applications requiring a high operatingvoltage.

The conventional DMOS device, whether it is a LDMOS or a VDMOS device,has limited capacity for increasing its breakdown voltage. Furthermore,the high ON-resistance (RON) of a conventional DMOS device is also asignificant problem waiting to be resolved.

SUMMARY OF THE INVENTION

Accordingly, at least one objective of the present invention is toprovide a high voltage metal oxide semiconductor (MOS) device having alower on-resistance.

At least another objective of the present invention is to provide amethod of fabricating a high voltage metal oxide semiconductor (MOS)device having a high breakdown voltage.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a high voltage metal oxide semiconductor (MOS)device. The high voltage MOS device comprises a substrate, an N-typeepitaxial layer, an isolation layer, a gate dielectric layer, a gate, anN-type drain region, a P-type well, an N-type source region, a firstN-type well and a buried N-doped region. The N-type epitaxial layer isdisposed on the substrate. The isolation structure is disposed in theN-type epitaxial layer. The gate dielectric layer is disposed on theN-type epitaxial layer adjacent to the isolation structure. The gate isdisposed on the gate dielectric layer and a portion of the isolationstructure. The N-type drain region is disposed in the N-type epitaxiallayer on that side of the gate close to the isolation structure. TheP-type well region is disposed in the N-type epitaxial layer on anotherside of the gate. The N-type source region is disposed in the P-typewell. The first N-type well is disposed in the N-type epitaxial layerunder the isolation structure on one side of the gate. Furthermore, thefirst N-type well and the N-type drain region have some overlappingarea. The buried N-doped region is disposed in the substrate under theN-type epitaxial layer and is connected to the first N-type well.

According to one preferred embodiment of the present invention, theaforementioned high voltage MOS device further includes an N-type driftregion disposed in the N-type epitaxial layer under the isolationstructure.

According to one preferred embodiment of the present invention, theN-type drift region of the high voltage MOS device has a dopantconcentration greater than the first N-type well.

According to one preferred embodiment of the present invention, theaforementioned high voltage MOS device further includes a second N-typewell disposed in the N-type epitaxial layer on that side of the gateclose to the isolation structure and is connected to the buried N-dopedregion. Furthermore, the second N-type well and the N-type drain regionhave some overlapping area.

According to one preferred embodiment of the present invention, thesecond N-type well of the high voltage MOS device has a dopantconcentration greater than the N-type drift region. Furthermore, theN-type drift region has a dopant concentration greater than the firstN-type well.

According to one preferred embodiment of the present invention, theaforementioned high voltage MOS device further includes a second N-typewell disposed in the N-type epitaxial layer on that side of the gateclose to the isolation structure and is connected to the buried N-dopedregion. Furthermore, the second N-type well and the N-type drain regionhave some overlapping area.

According to one preferred embodiment of the present invention, thesecond N-type well of the high voltage MOS device has a dopantconcentration greater than the first N-type well.

According to one preferred embodiment of the present invention, theisolation structure of the high voltage MOS device includes a fieldoxide layer.

The present invention also provides a method of fabricating a highpressure metal oxide semiconductor (MOS) device. First, a substrate isprovided. Then, a buried N-doped region is formed in the substrate.Thereafter, an N-type epitaxial layer is formed on the substrate. Afirst N-type well is formed in the N-type epitaxial layer such that thefirst N-type well is connected to the buried N-doped region. After that,an isolation structure is formed in the first N-type well. Then, a gatedielectric layer is formed on the N-type epitaxial layer. Thereafter, agate is formed over the gate dielectric layer and a portion of theisolation structure. Furthermore, a P-type well is formed in the N-typeepitaxial layer under a portion of the gate and on that side of the gateaway from the isolation structure. Then, an N-type drain region isformed in the N-type epitaxial layer on that side of the gate close tothe isolation structure. Finally, an N-type source region is formed inthe P-type well.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, themethod further includes forming an N-type drift region in the N-typeepitaxial layer under the isolation structure.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, theN-type drift region has a dopant concentration greater than the firstN-type well.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, themethod further includes forming a second N-type well in the N-typeepitaxial layer on that side of the gate close to the isolationstructure. The second N-type well is connected to the buried N-dopedregion. Furthermore, the second N-type well and the N-type drain regionhave some overlapping area.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, thesecond N-type well has a dopant concentration greater than the N-typedrift region and the N-type drift region has a dopant concentrationgreater than the first N-type well.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, themethod further includes forming a second N-type well in the N-typeepitaxial layer on that side of the gate close to the isolationstructure. The second N-type well is connected to the buried N-dopedregion. Furthermore, the second N-type well and the N-type drain regionhave some overlapping area.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, thesecond N-type well has a dopant concentration greater than the firstN-type well.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, theP-type well is formed before the gate or the P-type well is formed afterthe gate.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, theisolation structure includes a field oxide layer.

According to the aforementioned method of fabricating the high voltageMOS device in one preferred embodiment of the present invention, themethod of forming the field oxide layer includes performing a thermaloxidation.

Because the high voltage MOS device of the present invention has aburied N-doped region and various N-type regions with different dopantconcentrations, the breakdown voltage can be increased.

On the other hand, the buried N-doped region and the various N-typeregions with different dopant concentrations can provide the electriccharges with a greater number of more flow-paths so that theon-resistance can be reduced.

Furthermore, the method of fabricating the high voltage MOS deviceaccording to the present invention can be combined with existingbipolar-CMOS-DMOS process (or BCD process). Since there is no need tofabricated additional mask just to form the high voltage MOS devicestructure of the present invention, no additional production cost isincurred.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view of a conventional LDMOS.

FIG. 2 is a schematic cross-sectional view of a conventional VDMOSdevice.

FIGS. 3A through 3D are schematic cross-sectional views showing thesteps for fabricating a MOS transistor device according to one preferredembodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a high voltage MOS deviceaccording to one preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIGS. 3A through 3D are schematic cross-sectional views showing thesteps for fabricating a MOS transistor device according to one preferredembodiment of the present invention. As shown in FIG. 3A, a substrate300 is provided. The substrate 300 is an N-type silicon substrate, forexample.

Then, a buried N-doped region 302 is formed in the substrate 300. Themethod of forming the buried N-doped region 302 includes performing anion implant process using phosphorus as the dopants, for example.

Thereafter, an N-type epitaxial layer 304 is formed over the substrate300. The N-type epitaxial layer 304 is formed, for example, byperforming a chemical vapor deposition process with in-situ implant ofphosphorus dopants to form an amorphous silicon material layer (notshown) and performing an solid phase epitaxial process on the amorphoussilicon material layer thereafter.

As shown in FIG. 3B, an N-type well 306 is formed in the N-typeepitaxial layer 304 such that the N-type well 306 and the buried N-dopedregion 302 are connected. The N-type well 306 is formed, for example, byperforming an ion implant using phosphorus as the dopants.

Thereafter, an isolation structure 308 is formed in the N-type well 306.The isolation structure 308 is fabricated using silicon oxide, forexample. The isolation structure 308 is a field oxide layer formed, forexample, by performing a thermal oxidation. As anyone knowledgeable inthis area may notice that any structure or material with isolatingcapability can be used to form the isolation structure 308 in thepresent invention. For example, the isolation structure 308 can be ashallow trench isolation (STI) structure.

It should be noted that the high voltage MOS structure in the presentinvention might selectively form an N-type drift region 310 in theN-type epitaxial layer 304 under the isolation structure 308. The N-typedrift region 310 is formed, for example, by performing an ion implantprocess using phosphorus as the dopants. The N-type drift region 310 andthe N-type well 306 can be fabricated together in the same ion implantprocess by adjusting the ion implant energy and dopant concentration.The N-type drift region 310 has a dopant concentration greater than theN-type well 306.

In addition, an N-type well 312 can be selectively formed in the N-typeepitaxial layer 304 on that side close to the isolation structure 308such that the N-type well 312 is connected to the buried N-doped region302. The N-type well 306 is formed, for example, by performing an ionimplant process using phosphorus as the dopants. The N-type well 312 hasa dopant concentration greater than the N-type drift region 310.

As shown in FIG. 3C, a gate dielectric layer 314 is formed over theN-type epitaxial layer 304. The gate dielectric layer 314 is fabricatedusing silicon oxide, for example. The gate dielectric layer is formed,for example, by performing a thermal oxidation.

Thereafter, a gate 316 is formed over the gate dielectric layer 314 anda portion of the isolation structure 308. The gate 316 is fabricatedusing doped polysilicon, for example. The gate 316 is formed, forexample, by performing a chemical vapor deposition process with in-situdoping and performing a photolithographic and etching processthereafter.

Furthermore, an N-type source extension region 318 can also be formed inthe N-type epitaxial layer 304 on that side of the gate 316 away fromthe isolation structure 308. The N-type source extension region 318 isformed, for example, by performing an ion implant process usingphosphorus as the dopants.

Thereafter, spacers 320 are formed on the sidewalls of the gate 316. Thespacers 320 are fabricated using silicon nitride, for example. Thespacers 320 are formed, for example, by forming a spacer material layer(not shown) over the substrate and performing an etching back operationthereafter.

As shown in FIG. 3D, a P-type well 322 is formed in the N-type epitaxiallayer 304 on that side of the gate 316 away from the isolation structure308 and under a portion of the gate 316. The P-type well 322 is formed,for example, by performing an ion implant process using boron as thedopants. Although the P-type well 322 is formed after the gate 316,anyone familiar with the knowledge in this technical area may easilyinfer than the P-type well 322 can be formed before the gate 316.

Thereafter, an N-type drain region 324 is formed in the N-type epitaxiallayer 304 on that side of the gate 316 close to the isolation structure308 and an N-type source region 326 is formed in the P-type well 322.The N-type well 312 and the N-type drain region 324 have someoverlapping area. The N-type drain region 324 and the N-type sourceregion 326 are formed, for example, by performing an ion implant processusing phosphorus as the dopants.

The aforesaid method of forming the high voltage MOS device can becombined with the existing BCD process. Hence, additional photomask isnot required to fabricate the high voltage MOS device of the presentinvention.

FIG. 4 is a schematic cross-sectional view of a high voltage MOS deviceaccording to one preferred embodiment of the present invention. As shownin FIG. 4, the high voltage MOS device in the present inventioncomprises a substrate 300, a buried N-doped region 302, an N-typeepitaxial layer 304, an N-type well 306, an isolation structure 308, agate dielectric layer 314, a gate 316, a P-type well 322, an N-typedrain region 324 and an N-type source region 326. The N-type epitaxiallayer 304 is disposed on the substrate 300. The isolation structure 308is disposed in the N-type epitaxial layer 304. The gate dielectric layer314 is disposed on the N-type epitaxial layer 304 adjacent to theisolation structure 308. The gate 316 is disposed on the gate dielectriclayer 314 and a portion of the isolation structure 308. The N-type drainregion 324 is disposed in the N-type epitaxial layer 304 on that side ofthe gate 316 close to the isolation structure 308. The P-type well 322is disposed in the N-type epitaxial layer 304 on the other side of thegate 316. The N-type source region 326 is disposed in the P-type well322. The N-type well 306 is disposed under the isolation structure 308and in the N-type epitaxial layer 304 on one side of the gate 316.Furthermore, the N-type well 306 and the N-type drain region 324 havesome overlapping area. The buried N-doped region 302 is disposed in thesubstrate 300 under the N-type epitaxial layer 304 and connected to theN-type well 306.

It should be noted that an additional N-type drift region 310 might bedisposed in the N-type epitaxial layer 304 under the isolation structure308. The N-type drift region 310 has a dopant concentration greater thanthe N-type well 306.

In addition, an N-type well 312 may also be disposed in the N-typeepitaxial layer 304 on that side of the gate 316 close to the isolationstructure 308 such that the N-type well 312 is connected to the buriedN-doped region 302. The N-type well 312 and the N-type drain region 324have some overlapping area. The N-type well 312 has a dopantconcentration greater than the N-type drift region 310.

In one preferred embodiment, an N-type source extension region 318 mayalso be disposed in the N-type epitaxial layer 304 on that side of thegate 316 away from the isolation structure 308 and spacers 320 may bedisposed on the sidewalls of the gate 316.

Because the material of various film layers and their method offabrication as well as the method of fabricating various doped regionshave already been described, another detailed description is omittedhere.

Because the high voltage MOS device in the present invention includes avariety of N-type regions such as the buried N-doped region 302, theN-type well 306, the N-type drift region 310, the N-type well 312 eachwith a different dopant concentration, the breakdown voltage of thedevice is increased. In addition, the buried N-doped region 302 andvarious other N-doped regions with different dopant concentration canprovide the electric charges with more flow paths so that the overallon-resistance is reduced.

In summary, the major merits of the present invention at least includes:

1. The method used for fabricating the high voltage MOS device cancombine with the existing BCD process so that no additional mask has tobe manufactured. Hence, the high voltage MOS device of the presentinvention incurs no addition cost.

2. In the presence of the buried N-doped region and the various N-typeregions with different dopant concentration, the breakdown voltage ofthe high voltage MOS device is increased.

3. Furthermore, the presence of the buried N-doped region and thevarious N-type regions with different dopant concentration also provideselectric charges with more flow paths so that the on-resistance of thedevice is reduced.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A high voltage metal oxide semiconductor (MOS) device, comprising: asubstrate; an N-type epitaxial layer disposed on the substrate; anisolation structure disposed in the N-type epitaxial layer; a gatedielectric layer disposed on the N-type epitaxial layer and adjacent tothe isolation structure; a gate disposed on the gate dielectric layerand a portion of the isolation structure; an N-type drain regiondisposed in the N-type epitaxial layer on that side of the gate close tothe isolation structure; a P-type well disposed in the N-type epitaxiallayer on another side of the gate; an N-type source region disposed inthe P-type well; a first N-type well disposed under the isolationstructure and in the N-type epitaxial layer on one side of the gate,wherein the first N-type well and the N-type drain region have someoverlapping area; and a buried N-doped region disposed in the substrateunder the N-type epitaxial layer and connected to the first N-type well.2. The high voltage MOS device of claim 1, wherein the MOS devicefurther includes an N-type drift region disposed in the N-type epitaxiallayer under the isolation structure.
 3. The high voltage MOS device ofclaim 2, wherein the N-type drift region has a dopant concentrationgreater than the first N-type well.
 4. The high voltage MOS device ofclaim 2, wherein the MOS device further includes a second N-type welldisposed in the N-type epitaxial layer on that side of the gate close tothe isolation structure and connected to the buried N-doped region, andthe second N-type well and the N-type drain region have some overlappingarea.
 5. The high voltage MOS device of claim 4, wherein the secondN-type well has a dopant concentration greater than the N-type driftregion and the N-type drift region has a dopant concentration greaterthan the first N-type well.
 6. The high voltage MOS device of claim 1,wherein the MOS device further includes a second N-type well disposed inthe N-type epitaxial layer on that side of the gate close to theisolation structure and connected to the buried N-doped region, and thesecond N-type well and the N-type drain region have some overlappingarea.
 7. The high voltage MOS device of claim 6, wherein the secondN-type well has a dopant concentration greater than the first N-typewell.
 8. The high voltage MOS device of claim 6, wherein the isolationstructure includes a field oxide layer.